1. Field of the Invention
This invention relates to a bipolar transistor, and more particularly to a bipolar transistor with an improved integration and a reduced emitter-base parasitic capacitance.
2. Description of the Related Art
For the purpose of realizing higher integration density and increased speed operation, various types of bipolar transistors have been proposed. For example, U.S. Pat. No. 4,963,957 issued on Oct. 16, 1990 disclosed a process of forming self-aligned emitter and graft base regions, and bringing a collector connection conductor in direct contact with the buried n.sup.+ collector layer. This is distinguished from conventional bipolar transistors in which the buired n.sup.+ collector is in contact with a conductive layer of low resistivity buried in a trench provided in a semiconductor substrate. With this structure, the collector resistance is reduced, and the operation speed of the bipolar transistor is increased accordingly.
This prior art, however, paid no regard to the current distribution in the emitter region and had no concern with the location of the collector connection with respect to the emitter region. For this reason, the to reduction in the emitter-base parasitic capacitance is restricted to thereby lower an operation speed, and improvement in integration is also restricted.